Teaching Responsibility
LJMU Schools involved in Delivery:
LJMU Partner Taught
Learning Methods
Lecture
Tutorial
Workshop
Module Offerings
5503ICBTEL-APR-PAR
5503ICBTEL-JAN-PAR
5503ICBTEL-SEP_NS-PAR
Aims
This module introduce and develop a comprehensive understanding of the principles, procedures and applications of Digital System design based on PLDs and FPGAs.
Learning Outcomes
1.
Explain the top-down design process through the levels of abstraction from high-level system description down to gate-level and transistor level implementation.
2.
Apply various styles (behavioural, structural and physical) to describe the digital system in the hardware description language systems.
3.
Build behavioural and synthesis of Verilog-HDL descriptions of basic components and digital systems include combinational and sequential logic circuits and predict the behaviour of a digital system or the simulation result of a Verilog-HDL code.
4.
Apply Electronic Design Automation (EDA) tools and Hardware Description Languages to design and synthesize digital system(s) and apply on-chip debugging techniques for modern FPGA/CPLD-based hardware platforms such as Xilinx Spartan FPGA devices.
Module Content
Outline Syllabus:Digital system design process. EDA tools and design viewpoints. Behavioural, dataflow, and gate-level descriptions.
Hardware description languages. VHDL modelling concepts. Behavioural and structural architecture descriptions. Concurrent and sequential statements. Event-driven simulation.
Building blocks for digital systems: tri-state buffers, multiplexers, latches, flip-flops, registers, counters, arithmetic circuits, finite state machines.
Design methodology. Synchronous systems. Top down design. Register-transfer-level design. Test benches. Synthesis from VHDL.
Implementation issues: gate delays, timing, critical path, communication between unsynchronised machines, coping with metastability.
Introduction to Programmable Logic Devices (FPGAs, CPLDs).